This invention is in the field of semiconductor integrated circuits. Embodiments of this invention are directed to reduction of stress in the semiconductor material in certain device structures.
Recent advances in semiconductor technology as applied to integrated circuits include the use of “strain engineering” (or, alternatively, “stress engineering”) in the manufacture of semiconductor device structures. It has been discovered that the tuning of strain in the crystal lattice of metal-oxide-semiconductor (MOS) transistor channel regions can enhance carrier mobility in those regions. As is fundamental in MOS device technology, the source/drain current (i.e., drive) of an MOS transistor in both the triode and saturation regions is proportional to carrier mobility in the channel region. In a general sense, compressive stress enhances hole mobility in the channel region of a p-channel MOS transistor, and tensile stress enhances electron mobility in the channel region of an n-channel MOS transistor. Typically, p-channel MOS transistors exhibit lower drive capability than n-channel MOS transistors in typical modern integrated circuits. As such, strain engineering techniques are more typically applied to p-channel MOS transistors than to n-channel MOS transistors, in current day manufacturing technology.
Various strain engineering approaches are known in the art. According to the approach known as “embedded SiGe” (also referred to as “eSiGe”), the source and drain regions of a p-channel MOS transistor structure are etched from the silicon substrate or well region, and are replaced with a silicon-germanium alloy formed by selective epitaxy. Because of the germanium atoms within the crystal lattice, the germanium constituting as much as 30% (atomic) of the alloy, eSiGe exhibits a larger lattice constant than does silicon (i.e., the distance between unit cells in the crystal lattice for SiGe is greater than in single-crystal silicon). Embedded eSiGe source/drain regions thus apply compressive stress to the channel region of the p-channel MOS transistor being formed. This compressive stress in the channel increases the hole mobility of the p-channel MOS transistor, and enhances its performance.
FIGS. 1a through 1d illustrate, in cross section, the fabrication of a conventional p-channel MOS transistor including eSiGe source/drain regions. FIG. 1a illustrates a portion of the integrated circuit structure including p-type substrate 4, with n-well 6 formed at selected locations of the surface of substrate 4, by way of ion implantation and diffusion in the conventional manner. Shallow trench isolation structures 5 are disposed at selected locations of the surface of substrate 4, formed by conventional etch and deposition processes. Dopant implant to adjust the threshold voltage of the eventual transistor is typically also performed at this stage of manufacture. At the stage of the process shown in FIG. 1b, thermal oxidation or deposition of gate dielectric 7 has been followed by the deposition, photolithography, and etch of polysilicon gate structure 8. In this example, hard mask 9 is used to protect polysilicon gate structure 8 from the polysilicon etch, and remains in place.
To form the embedded SiGe source/drain regions in this conventional process, gate dielectric 7 is removed from the source/drain regions, and exposed locations of n-well 6 are etched, at locations outside of gate electrode 8, to form recesses 10 into the underlying single-crystal silicon, as shown in FIG. 1c. Hard mask 9 protects gate structure 8 from the recess etch, but is eroded somewhat by this etch. Recesses 10 are thus located at the source/drain regions of the transistor being formed at this location of substrate 4, essentially self-aligned with gate structure 8. Following the recess etch, selective epitaxy of a silicon-germanium alloy is then performed, filling the recesses with embedded SiGe structures 12 as shown in FIG. 1d. SiGe structures 12 are typically doped in situ during the epitaxy, and also by subsequent ion implantation, to become heavily doped p-type, forming the source and drain regions of this transistor. Sidewall dielectric spacers 13 may be formed prior to source/drain implant on the sidewalls of gate structure 8, by deposition and anisotropic etch, to define more lightly-doped source/drain extensions.
As suggested in FIG. 1d, embedded SiGe structures 12 exert compressive strain on channel region 14 underlying gate electrode 8, because the presence of germanium atoms increases the lattice constant of SiGe structures 12 relative to the surrounding silicon. This compressive strain increases the mobility of holes in channel region 14, enhancing the current drive of this p-channel transistor in an “on” state.
By way of further background, many integrated circuits include “guard ring” structures. Guard rings are typically formed as a diffused region surrounding one or more transistors or other devices in the integrated circuit, and to which contact is made via metal or another conductor to reverse bias the p-n junction between the guard ring and the substrate or well into which it is formed. Guard rings have many purposes in conventional integrated circuits, including decoupling external noise from reaching the protected devices interior of the guard ring, providing a large junction area for purposes of dissipating energy from electrostatic discharge (ESD) events, and, when present at the perimeter of the integrated circuit chip, presenting a barrier to ionic contamination entering from the edges of the chip.